SC is the International Conference for
 High Performnance Computing, Networking, Storage and Analysis

SCHEDULE: NOV 13-19, 2010

Mapping Your Application on Interconnect Topologies: Effort versus Benefits

SESSION: George Michael HPC Fellowship Awardee Presentations

EVENT TYPE: George Michael HPC Fellow Presentation

TIME: 1:30PM - 2:15PM


Presenter(s):Abhinav Bhatele


Petascale machines with hundreds of thousands of cores are being built. These machines have varying interconnect topologies and large network diameters. Computation is cheap and communication on the network is becoming the bottleneck for strong scaling of parallel applications. Most parallel applications typically have a certain communication topology. Mapping of tasks in a parallel application based on their communication graph, to the physical processors on the machine can potentially lead to performance improvements. Mapping of the communication graph for an application on to the interconnect topology of a machine while trying to localize communication is the research problem under consideration. Performance improvements for applications such as WRF and NAMD will be presented to motivate the work. Building on these ideas, the talk will discuss algorithms and techniques for automatic mapping of parallel applications to relieve the application developers of this burden. The automatic mapping framework is a suite of algorithms with capabilities to choose the best mapping for a problem with a given communication graph. This framework will save much effort on the part of application developers to generate mappings for their individual applications. More details on my research available at:

Chair/Presenter Details:

Mark Hoemmen (Chair) - Sandia National Laboratories

Abhinav Bhatele - University of Illinois at Urbana-Champaign

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