SC is the International Conference for
 High Performnance Computing, Networking, Storage and Analysis

SCHEDULE: NOV 13-19, 2010

The 48-Core SCC Processor: The Programmer’s View

SESSION: Programming Models


TIME: 2:00PM - 2:30PM

SESSION CHAIR: Kenjiro Taura

AUTHOR(S):Tim Mattson, Rob Van der Wijngaart, Michael Riepen, Thomas Lehnig, Paul Brett, Werner Haas, Patrick Kennedy, Jason Howard, Sriram Vangal, Nitin Borkar, Greg Ruhl, Saurabh Dighe


The number of cores integrated onto a single die is expected to climb steadily in the foreseeable future. This move to many-core chips is driven by a need to optimize performance per watt. How to best connect these cores and how to program the resulting many-core processor, however, is an open research question. Designs vary from GPUs to cache-coherent shared memory multiprocessors to pure distributed memory chips. The 48-core SCC processor reported in this paper is an intermediate case sharing traits of message passing and shared memory architectures. The hardware has been described elsewhere. In this paper, we describe the programmer’s view of this chip. In particular we describe RCCE: the native message passing model created for the SCC processor.

Chair/Author Details:

Kenjiro Taura (Chair) - University of Tokyo

Tim Mattson - Intel Corporation

Rob Van der Wijngaart - Intel Corporation

Michael Riepen - Intel Corporation

Thomas Lehnig - Intel Corporation

Paul Brett - Intel Corporation

Werner Haas - Intel Corporation

Patrick Kennedy - Intel Corporation

Jason Howard - Intel Corporation

Sriram Vangal - Intel Corporation

Nitin Borkar - Intel Corporation

Greg Ruhl - Intel Corporation

Saurabh Dighe - Intel Corporation

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The full paper can be found in the ACM Digital Library and IEEE Computer Society

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