SC is the International Conference for
 High Performnance Computing, Networking, Storage and Analysis

SCHEDULE: NOV 13-19, 2010

On-Chip Network Evaluation Framework

SESSION: On-Chip Networks and Power Management

EVENT TYPE: Paper, Best Student Paper (BSP) Finalist

TIME: 10:30AM - 11:00AM

SESSION CHAIR: Keren Bergman

AUTHOR(S):Hanjoon Kim, Seulki Heo, Junghoon Lee, Jaehyuk Huh, John Kim

ROOM:391-392

ABSTRACT:
With the number of cores on a chip continuing to increase, proper evaluation of on-chip network is critical for not only network performance but also overall system performance. In this paper, we show how a network-only simulation can be limited as it does not provide an accurate representation of system performance. We evaluate traditionally used open-loop simulations and compare them to closed-loop simulations. Although they use different methodologies, measurements, and metrics, we identify how they can provide very similar results. However, we show how the results of closed-loop simulations do not correlate well with execution-driven simulations. We then add simple extensions to the closed-loop simulation to model the impact of the processor and the memory system and show how the correlation with execution-driven simulations can be improved. The proposed framework/methodology provides a fast simulation while providing better insights into the impact of network parameters on overall system performance.

Chair/Author Details:

Keren Bergman (Chair) - Columbia University

Hanjoon Kim - Korea Advanced Institute of Science & Technology

Seulki Heo - Korea Advanced Institute of Science & Technology

Junghoon Lee - Korea Advanced Institute of Science & Technology

Jaehyuk Huh - Korea Advanced Institute of Science & Technology

John Kim - Korea Advanced Institute of Science & Technology

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The full paper can be found in the ACM Digital Library and IEEE Computer Society

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