SC is the International Conference for
 High Performnance Computing, Networking, Storage and Analysis

SCHEDULE: NOV 13-19, 2010

A Performance Tuning Strategy under Combining Loop Transformations for a Vector Processor with an On-Chip Cache

SESSION: Research Poster Reception

EVENT TYPE: Poster

TIME: 5:15PM - 7:00PM

AUTHOR(S):Yoshiei Sato, Ryuichi Nagaoka, Akihiro Musa, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi

ROOM:Main Lobby

ABSTRACT:
Recently the ratio of memory bandwidth to computational performance (B/F) of vector processors has decreased. To cover the insufficient B/F, an on-chip cache is employed by modern vector processors. The purpose of this work is to establish the performance tuning strategy for the vector processor with vector cache to exploit its potential. In the strategy, loop unrolling and cache blocking which are the important loop transformations for optimization are combined systematically to break the performance bottleneck. To decide which of loop unrolling and cache blocking is performed first, the roofline model is employed as the performance model. Then the optimization effective to remove the bottleneck is applied preferentially. To determine the number of loop unrolls and the blocking size, we employ the greedy search algorithm. The superiority of the strategy is evaluated several applications. The evaluation results show that the proposal improves the performance and reduce the energy consumption drastically.

Chair/Author Details:

Yoshiei Sato - Tohoku University

Ryuichi Nagaoka - Tohoku University

Akihiro Musa - NEC Corporation

Ryusuke Egawa - Tohoku University

Hiroyuki Takizawa - Tohoku University

Koki Okabe - Tohoku University

Hiroaki Kobayashi - Tohoku University

Add to iCal  Click here to download .ics calendar file

Add to Outlook  Click here to download .vcs calendar file

Add to Google Calendarss  Click here to add event to your Google Calendar

   Sponsors    IEEE    ACM