SC is the International Conference for
 High Performnance Computing, Networking, Storage and Analysis

SCHEDULE: NOV 13-19, 2010

How to Analyze the Performance of Parallel Codes 101: A Case Study with Open|SpeedShop

SESSION: S01: How to Analyze the Performance of Parallel Codes 101: A Case Study with Open|SpeedShop

EVENT TYPE: Tutorial

TIME: 8:30AM - 12:00PM

Presenter(s):Martin Schulz, Jim Galarowicz, David Montoya, Mahesh Rajan, Don Maghrak

ROOM:389

ABSTRACT:
Performance analysis is an essential step in the development of HPC codes. It will even gain in importance with the rising complexity of machines and applications that we are seeing today. Many tools exist to help with this analysis, but the user is too often left alone with interpreting the results. In this tutorial we will provide a practical road map for the performance analysis of HPC codes and will provide users step by step advice on how to approach the optimization of their codes as well as on how to investigate observed performance bottlenecks in detail. We will cover both on-node performance and communication optimization. Throughout this tutorial will show live demos using Open|SpeedShop, a comprehensive and easy to use performance analysis tool set, to demonstrate the individual analysis steps. All techniques will, however, apply broadly to any tool and we will point out alternative tools where useful.

Chair/Presenter Details:

Martin Schulz - Lawrence Livermore National Laboratory

Jim Galarowicz - Krell Institute

David Montoya - Los Alamos National Laboratory

Mahesh Rajan - Sandia National Laboratories

Don Maghrak - Krell Institute

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